FIG. 1 illustrates in schematic diagram form six-transistor memory cell 10 according to the prior art. Memory cell 10 includes N-channel transistors 11 and 12, P-channel transistors 13 and 14, and N-channel pass transistors 15 and 16. The gates of N-channel transistor 11 and P-channel transistor 13 are connected to node 102. The gates of N-channel transistor 12 and P-channel transistor 14 are connected to node 101. N-channel pass transistor 15 has a first current electrode connected to node 101 and a second current electrode connected to bit line 17 labeled "BL". N-channel pass transistor 16 has a first current electrode connected to node 102 and a second current electrode connected to bit line 18 labeled "BL*". (Note that an asterisk "*" after a signal or line name indicates that the signal or line is a logical complement of a signal or line having the same name but lacking the asterisk "*".) The gates of N-channel pass transistors 15 and 16 are connected to word line 19 labeled "WL". N-channel pass transistors 15 and 16 couple nodes 101 and 102, respectively, to bit lines 17 and 18 when word line 19 is enabled as a logic high. The sources of P-channel transistors 13 and 14 are connected to a positive power supply voltage terminal labeled "V.sub.DD ". The source of each of N-channel transistors 11 and 12 is connected to a negative power supply voltage terminal labeled "V.sub.SS ". V.sub.SS is normally at ground potential and V.sub.DD receives a power supply voltage of about 3.3 volts. A power supply voltage of about 3.3 volts may range between about 3.0 volts and about 3.6 volts.
N-channel transistors 11 and 12 and P-channel transistors 13 and 14 form a cross-coupled latch. Memory cell 10 stores a data bit based on the voltages at nodes 101 and 102. Reading and writing to memory cell 10 is accomplished through bit lines 17 and 18. To write data into memory cell 10, word line 19 is enabled as a logic high and complementary data signals are applied to bit lines 17 and 18 at a potential high enough to overwrite the contents of the memory cell. The voltage on bit lines 17 and 18 is approximately at the potential of V.sub.DD for a logic high and near V.sub.SS for a logic low. Memory cell 10 will latch in either a logic high or a logic low state depending on the logic states of bit lines 17 and 18.
Assuming bit line 17 is a logic high and bit line 18 is a logic low when word line 19 is enabled, N-channel pass transistors 15 and 16 are both conductive. The logic states of bit lines 17 and 18 are provided to nodes 101 and 102. Node 101 becomes a logic high, causing P-channel transistor 14 to become substantially non-conductive and N-channel transistor 12 to become conductive. Node 102 is reduced to a logic low voltage equal to approximately the negative power supply voltage. P-channel transistor 13 is conductive, and N-channel transistor 11 is non-conductive. Initially, a logic high voltage at node 101 is approximately equal to the positive power supply voltage minus a threshold voltage drop (V.sub.T) across P-channel transistor 13. The voltage at node 101 will eventually rise to approximately the potential of V.sub.DD. The V.sub.T across P-channel transistor 13 is equal to approximately 0.8 volts with a power supply voltage of 3.3 volts.
During a read cycle of memory 30, word line 19 is enabled, causing N-channel pass transistors to be conductive. Column logic/decoders select bit lines 17 and 18 to read the data bit stored in memory cell 10. The latched logic states stored on nodes 101 and 102 are provided to bit lines 17 and 18 as a relatively low differential voltage, (approximately 50-100 millivolts). During a read cycle, the logic states of nodes 101 and 102 remain unchanged.
Memory cell 10 maintains the current logic state for as long as a power supply voltage is provided. However, memory cell 10 may inadvertently change logic states due to charged particle emissions. These charged particles include alpha particles, x-rays, or other sources of ionizing radiation. Alpha particles are emitted as a result of the natural radioactive decay of radioactive elements such as uranium, americium, and thorium. Uranium and thorium are sometimes present in semiconductor packaging material in small amounts. Radioactive elements may also be present in the aluminum layers of the integrated circuit. The alpha particles are emitted from the radioactive elements and penetrate the memory array region of the SRAM cell. An alpha particle striking in the vicinity of memory cell 10 may change the logic state of the cell. When an alpha particle strikes the integrated circuit, electrons migrate toward the most positive sources. The charge from the alpha particle strike may be large enough to cause memory cell 10 to change logic states. This is called a soft error. A soft error is difficult to detect because the memory cell changes logic states without suffering any physical damage.
The critical charge (Q.sub.CRIT) required to cause memory cell 10 to change logic states is equal to the product of the change in voltage as a result of the alpha particle hit (.DELTA.V.sub..alpha.), and the cell capacitance (C.sub.CELL), or EQU Q.sub.CRIT =.DELTA.V.sub..alpha. C.sub.CELL ( 1)
Various techniques have been found to reduce soft error in memory cell 10. For instance, soft error is sometimes reduced by increasing cell capacitance C.sub.CELL. Cell capacitance C.sub.CELL is increased by adding capacitance to N-channel transistors 11 and 12 of memory cell 10, or by coupling capacitors between each of nodes 101 and 102 and V.sub.SS. Q.sub.CRIT should be made large enough to withstand the charge leakage caused by an alpha particle hit. However, write speed may be sacrificed if cell capacitance C.sub.CELL is too large. Increasing Q.sub.CRIT by adding capacitance increases the voltage change .DELTA.V.sub..alpha. required to cause memory cell 10 to change logic states. But, adding capacitance to memory cell 10 increases process constraints and may increase the surface area required for each SRAM cell.
As the density and size of SRAMs are increased, memory cell sizes reduced, and power supply voltage decreased, memory cell 10 becomes even more vulnerable to soft error. Also, P-channel transistors 64 and 65 may be thin film transistor (TFT) loads. TFT transistors provide the advantages of low standby current and good cell stability without increasing cell size. However, the small size of a TFT transistor results in decreased cell capacitance, which also may cause increased soft error. Thus, in a very high density SRAM, as memory cell size is reduced, it becomes harder to increase cell capacitance C.sub.CELL without negating, at least in part, the reduction in size.